1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a circuit for controlling an internal voltage for output buffer portions of a semiconductor memory device, and a method therefor.
2. Description of the Related Arts
With the recent trend towards increasing the integration of semiconductor memory devices, the data output speed and bandwidth increases. In particular, as a burst operation which is a kind of output mode of a synchronous DRAM becomes important, the gap between the output hold time (tOH) and the data output time (tSAC) becomes an important parameter. When the gap is added to the determined output hold time and data output time, it becomes the cycle time (tCC). Accordingly, the cycle time (tCC) increases with the increase of the gap. When cycle time increases, the bandwidth of the semiconductor memory device decreases, which is not desirable.
The gap between the output hold time and the data output time increases due to variations in a supply voltage (Vcc), a temperature or process parameters and a variation in electrical characteristics between output pins, etc. Among them, variations in the supply voltage change and the temperature are critical. The increase in the gap due to the supply voltage change is reduced by use of an internal voltage generator for an output buffer. Since the internal voltage generator which is used only for output buffers is not much influenced by the variation of an external supply voltage, e.g., voltage ranging from 3.0 V to 3.6 V, it can provide current at a relatively constant level to output buffers. In order to control the current supply capability, an internal voltage controlling circuit can be used.
FIG. 1 is a block diagram for explaining a conventional internal voltage controlling circuit in a semiconductor memory device. In FIG. 1, an internal voltage control circuit 17 of a semiconductor memory device 11 is drawn along with first to eighth output buffers 21 to 28. Even though FIG. 1 shows eight output buffers 21 through 28 and two internal voltage generators 13 and 15, 32 output buffers and 4 internal voltage generators may be used, instead.
The internal voltage control circuit 17 includes the first and second internal voltage generators 13 and 15. The internal voltage control circuit 17 receives an external control signal (EN) and generates an internal voltage (IVC). When the external control signal (EN) is active, each of the first and second internal voltage generators 13 and 15 generates a predetermined internal voltage (IVC). The internal voltage (IVC) is a voltage which is required to operate the first to eighth output buffers 21 to 28. The first to eighth output buffers 21 to 28 receive the internal voltage (IVC) and generate data signals D0 to D7, respectively, to the outside of the semiconductor memory device 11. That is, data DOUT0 to DOUT7 are generated by the first to eighth output buffers 21 to 28, respectively.
FIG. 2 is a circuit diagram of the first and second internal voltage generators 13 and 15. Since the first and second internal voltage generators 13 and 15 have the same structures, only the first internal voltage generator 13 will now be described, in order to avoid duplication of the explanation.
Referring to FIG. 2, the first internal voltage generator 13 is comprised of a differential amplifier, which includes a comparing unit 31 and a current source 33. The current source 33 is comprised of an NMOS transistor 41 the gate of which receives the external control signal (EN). Accordingly, when the external control signal (EN) is active, i.e., at a logic high level, the NMOS transistor 41 is activated. Therefore, a constant current flows from the comparing unit 31 into a ground (GND), so that the NMOS transistor 41 serves as a current source.
The comparing unit 31 includes two NMOS transistors 43 and 45 and three PMOS transistors 47, 49 and 51. A reference voltage (VREF) and the internal voltage (IVC) are applied to the gates of the NMOS transistors 43 and 45, respectively. The two NMOS transistors 43 and 45 compare the two voltages, and the transistor having the higher voltage applied to its gate is turned on harder. That is, when the reference voltage (VREF) is higher than the internal voltage (IVC), the NMOS transistor 43 is turned on harder. On the other hand, when the internal voltage (IVC) is higher than the reference voltage (VREF), the NMOS transistor 45 is turned on harder. By "activated" we mean the device is turned on more than the other device of the pair; they operate in complementary fashion as the total current (through 41) is constant, as further explained below.
Now, the overall operations of the first internal voltage generator 13 shown in FIG. 2 will be described. The external control signal (EN) is activated to a logic high level during reading operation of the semiconductor memory device 11. When the external control signal (EN) is active, the NMOS transistor 41 is activated. Then, the NMOS transistor 43 is activated by the reference voltage (VREF), so that the voltage of a node (N1) decreases. Then, a PMOS transistor 51 is activated, so that the internal voltage (IVC) is pulled up toward to a supply voltage (VCC) level.
When the internal voltage (IVC) becomes higher than the reference voltage (VREF), however, the NMOS transistor 45 is activated. When the NMOS transistor 45 is activated, the voltage of a node (N2) is pulled down. Thus, both of PMOS transistors 47 and 49 are activated. Then, since the voltage level of the node (N1) is increased, the PMOS transistor 51 is deactivated. As the PMOS transistor 51 is deactivated, the voltage level of the internal voltage (IVC) decreases due to the change consumption of the output buffers 21 through 28.
Therefore, according to the degree to which the NMOS transisters 43 and 45 are turned on the internal voltage is output. The second internal voltage generator 15 operates in the same way as the first internal voltage generator 13, and generates an internal voltage having the same level as that of the internal voltage generated by the first internal voltage generator 13 when the external control signal (EN) is activated.
As described above, in the prior art, when the external control signal (EN) is activated, both the first and second internal voltage generators 13 and 15 are both operated so that an internal voltage (IVC) is generated. Even when only the first to fourth output buffers 21 to 24 are used, both the first and second internal voltage generators 13 and 15 generate an internal voltage. As a result, the current supplying capability to the first to fourth output buffers 21 to 24 becomes twice the current supplying capability which would flow when all the first to eighth output buffers 21 to 28 are used. In other words, the current supplying capability to each output buffer increases when the number of output buffers decreases, while the current supplying capability to each output buffer decreases when the number of output buffers increases. Thus, the internal voltage control circuit can not provide a constant current. Furthermore, when the number of output buffers is small, power consumption of the internal voltage generators is increased unnecesarily since both the internal voltage generators are operated.